NDLI: NBTI mitigation by optimized NOP assignment and insertion

Content Provider	IEEE Xplore Digital Library
Author	Firouzi, F. Kiamehr, S. Tahoori, M.B.
Copyright Year	2012
Description	Author affiliation: Dependable Nano-Computing (CDNC), Karlsruhe Institute of Technology (KIT), 76131, Germany (Firouzi, F.; Kiamehr, S.; Tahoori, M.B.)
Abstract	Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.
Starting Page	218
Ending Page	223
File Size	275938
Page Count	6
File Format	PDF
ISBN	9781457721458
ISSN	15301591
DOI	10.1109/DATE.2012.6176465
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-12
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Program processors Delay Degradation Logic gates Registers Hazards Transistors
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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