NDLI: Reduction of test power and data volume in BIST scheme based on scan slice overlapping

Content Provider	IEEE Xplore Digital Library
Author	Zhou Bin Ye Yi-zheng Wu Xin-chun Li Zhao-lin
Copyright Year	2009
Description	Author affiliation: Microelectronics Center, Harbin Institute of Technology, China (Zhou Bin; Ye Yi-zheng; Wu Xin-chun) \|\| School of Information Science and Technology, Tsinghua University, Beijing, China (Li Zhao-lin)
Abstract	In order to further reduce test data storage and test power of deterministic BIST based on LFSR reseeding and scan slice overlapping scheme, two optimization algorithms are proposed. One algorithm is to reorder scan cell by random exchanging two scan cells considering layout constraint in every loop. If both the number of specified bits and the number of overlapping blocks after exchanging operation are decreased, the exchanging operation is kept, otherwise the exchanging operation is ignored. The other algorithm is to partition test patterns by selecting the scan slice with most specified bits as the first scan slice of the current overlapping block. In this way, the partition which can lead to the minimal number of overlapping blocks and the minimal number of specified bits can be always achieved. Combining the proposed algorithms, test power and even test data storage can be significantly reduced. Experimental results indicate that the proposed method significantly reduces the switching activity and test data storage by 72%–92% and 54%–91%, respectively.
Starting Page	2737
Ending Page	2740
File Size	703584
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118368
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Memory Automatic testing Partitioning algorithms Flip-flops Test pattern generators Very large scale integration Circuit faults Microelectronics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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