NDLI: Evaluation of Simple/Comparative Power Analysis against an RSA ASIC implementation

Content Provider	IEEE Xplore Digital Library
Author	Miyamoto, A. Homma, N. Aoki, T. Satoh, A.
Copyright Year	2009
Description	Author affiliation: National Institute of Advanced Industrial Science and Technology, 1-18-13 Sotokanda, Chiyoda-ku, Tokyo, 101-0021 Japan (Satoh, A.) \|\| Graduate School of Information Sciences, Tohoku University, 6-6-05, Aramaki Aza Aoba, Aoba-ku, Sendai-shi 980-8579, Japan (Miyamoto, A.; Homma, N.; Aoki, T.)
Abstract	Simple Power Analysis attacks with chosen-message techniques were applied to an RSA processor implemented with standard CMOS technology on ASIC, and the different characteristics of power waveforms caused by two types of implementation (ASIC and FPGA) were investigated in detail. We also applied Comparative Power Analysis an advanced power analysis attack in which a pair of input data was used to enhance the waveform pattern for modular exponentiation. The power dissipation of modular squaring in the difference waveform was greatly reduced when compared to modular multiplication, allowing all of the secret key bits to be successfully revealed.
Starting Page	2918
Ending Page	2921
File Size	2408906
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Public key cryptography CMOS technology Algorithm design and analysis Field programmable gate arrays Information analysis CMOS process Pattern analysis Power dissipation Electromagnetic radiation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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