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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Alioto, M. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of Information Engineering, University of Siena, Italy (Alioto, M.) |
| Abstract | In this paper, loading effects associated with uniform RC interconnects are analytically modeled to deeply understand the effects that contribute to their input admittance. A simple reduced-order model is developed and shown to be accurate by means of simulations on a 65-nm CMOS technology. The resulting analytical expression of the model permits a deeper understanding of the loading effects of RC uniform wires on the driving circuit (e.g., the previous repeater). The model is also simple enough to be used in fast and accurate estimations in automated CAD tools. Interestingly, analysis allows for identifying a new circuit effect, the so-called “capacitive shielding” effect. This effect consists in the reduction of the effective resistance (and capacitance) that is seen at the input of the interconnect, due to the wire and load capacitances. Interestingly, the capacitive effect is shown to be the dual of the well-known “resistive shielding” effect associated with RC interconnects, which determines a reduction in the effective capacitance due to the wire resistance. |
| Starting Page | 2269 |
| Ending Page | 2272 |
| File Size | 815656 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424438273 |
| DOI | 10.1109/ISCAS.2009.5118251 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-24 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitance Integrated circuit interconnections Wire Semiconductor device modeling Admittance Repeaters Timing CMOS technology Impedance Energy consumption |
| Content Type | Text |
| Resource Type | Article |
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