NDLI: Low area Elliptic Curve arithmetic unit

Content Provider	IEEE Xplore Digital Library
Author	Fournaris, A.P. Koufopavlou, O.
Copyright Year	2009
Description	Author affiliation: Electrical and Computer Engineering Dpt, University of Patras, Greece (Koufopavlou, O.) \|\| Electrical and Computer Engineering Dpt, Computer Engineering and Informatics Dpt., University of Patras, Greece (Fournaris, A.P.)
Abstract	In this paper, a generic Elliptic Curve (EC) arithmetic unit with high flexibility and small chip covered area is proposed. This EC arithmetic unit is based on the one dimensional systolic architectural realization of a proposed modified multiplication - inversion algorithm that through appropriate initialization uses the algorithmic structure of inversion to also perform multiplication. The proposed architecture is realized on FPGA for GF(2163) and is compared with similar up-to-date designs. The proposed EC arithmetic unit has very small chip covered area without any serious penalty in calculation delay and since is designed on the affine coordinate plane, it offers a good side channel attack resistance base for further optimizations on this field.
Starting Page	1397
Ending Page	1400
File Size	767471
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118026
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Elliptic curves Hardware Elliptic curve cryptography Field programmable gate arrays Digital arithmetic Delay Design optimization Algorithm design and analysis Information security Power system security
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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