NDLI: Surge current minimization in high-level synthesis

Content Provider	IEEE Xplore Digital Library
Author	Jheng-Fu Yeh Chun-Hua Cheng Shih-Hsu Huang
Copyright Year	2009
Description	Author affiliation: Department of Electronic Engineering, Chung Yuan Christian University, Chung Li, Taiwan, R.O.C. (Jheng-Fu Yeh; Chun-Hua Cheng; Shih-Hsu Huang)
Abstract	Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis (including operation scheduling and functional unit binding) has a great impact on the maximum surge current. Then, based on that observation, we propose an integer linear program (ILP) to formally draw up the surge current minimization problem in the high-level synthesis stage. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.
Starting Page	1513
Ending Page	1516
File Size	801571
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surges High level synthesis Circuits Minimization Clocks Energy consumption Timing Power engineering and energy CMOS process CMOS technology
Content Type	Text
Resource Type	Article

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