NDLI: Multi-Split-Row Threshold decoding implementations for LDPC codes

Content Provider	IEEE Xplore Digital Library
Author	Mohsenin, T. Truong, D. Baas, B.
Copyright Year	2009
Description	Author affiliation: ECE Department, University of California, Davis, USA (Mohsenin, T.; Truong, D.; Baas, B.)
Abstract	The recently introduced Split-Row Threshold algorithm significantly improves the error performance when compared to the non-threshold Split-Row algorithm while requiring a very small increase in hardware complexity. The Multi-Split-Row Threshold decoding algorithm presented in this paper enables further reductions in routing complexity for greater throughput and smaller circuit area implementations. Several Multi-Split-Row Threshold decoder designs have been implemented in 65 nm CMOS and the impact of the different levels of partitioning on error performance, wire interconnect complexity, decoder area, and speed are investigated. The Split-Row-16 Threshold decoder occupies 3.8 $mm^{2},$ runs at 100 MHz, delivers a throughput of 13.8 Gbps at 15 iterations and is only 0.28 dB and 0.22 dB away from SPA and MinSum Normalized.
Starting Page	2449
Ending Page	2452
File Size	708498
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118296
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Iterative decoding Integrated circuit interconnections Partitioning algorithms Wire Iterative algorithms Throughput Message passing Digital video broadcasting Hardware
Content Type	Text
Resource Type	Article

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