NDLI: High efficiency architecture of ESCOT with Word-Level pass concurrent context modeling scheme for SVC

Content Provider	IEEE Xplore Digital Library
Author	Jen-Shiun Chiang Ting-Hao Hwang Tsung-Ta Lin Kuang-Che Teng
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan (Jen-Shiun Chiang; Ting-Hao Hwang; Tsung-Ta Lin; Kuang-Che Teng)
Abstract	In this work, we propose a high efficiency hardware architecture of embedded sub-band coding with optimal truncation (ESCOT) with word-level pass concurrent context modeling (Word-Level PCCM) scheme for wavelet-based scalable video coding (SVC). Word-Level PCCM can merge the three-pass process of bit-plane coding into a single pass process. It improves the efficiency of the ESCOT algorithm and reduces the memory requirement and the memory access frequency. Furthermore the parallel architecture scheme for Word-Level PCCM can encode 8 samples concurrently. We use the Artison TSMC 0.18µm 1P6M standard cell library to design and implement the proposed Word-Level PCCM. The simulation results indicate that the Word-Level PCCM can operate for 1080p with frame rate of 60fps at clock rate of 125MHz.
Starting Page	1061
Ending Page	1064
File Size	989229
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5117942
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Context modeling Static VAr compensators Hardware Video sequences Video coding Video compression Discrete wavelet transforms Wavelet analysis Entropy coding Encoding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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