NDLI: Analysis and design of ultra-low power subthreshold MCML gates

Content Provider	IEEE Xplore Digital Library
Author	Alioto, M. Leblebici, Y.
Copyright Year	2009
Description	Author affiliation: Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Switzerland (Leblebici, Y.) \|\| Department of Information Engineering, University of Siena, Italy (Alioto, M.)
Abstract	In this paper, ultra-low power current-mode subthreshold MOS Current-mode Logic (MCML) gates are discussed from a modeling and design perspective. A detailed analysis of the DC characteristics is presented, and the effect of process variations is analyzed in depth. Analysis allows for understanding the main limits of sub-threshold MCML gates in terms of delay/power variability. In particular, it is shown that process variations strongly affect the DC characteristics, and moderately impact delay and power consumption. Interestingly, delay and power variations are shown to be significantly reduced compared to typical values encountered in standard subthreshold CMOS logic. Criteria to size transistors to keep variations within assigned bounds are also derived. Results of Monte Carlo simulations with a 65-nm CMOS technology are reported to validate theoretical results.
Starting Page	2557
Ending Page	2560
File Size	874879
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS logic circuits Delay CMOS technology Energy consumption Threshold voltage Logic circuits Semiconductor device modeling MOSFETs Information analysis Design engineering
Content Type	Text
Resource Type	Article

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