NDLI: Leakage reduction in FPGA routing multiplexers

Content Provider	IEEE Xplore Digital Library
Author	Hasan, M. Kureshi, A.K. Arslan, T.
Copyright Year	2009
Description	Author affiliation: School of Engineering and Electronics, University of Edinburgh, King's Buildings, United Kingdom (Arslan, T.) \|\| Department of Electronics Engineering, AMU, Aligarh, India (Hasan, M.; Kureshi, A.K.)
Abstract	There is a pressing need to reduce the static power consumption in FPGAs implemented in deep submicron so that it can also be used in portable battery operated devices. The multiplexer based interconnect matrix of an FPGA consumes most of the static power consumption. This paper investigates reducing leakage power in unused FPGA routing multiplexers by controlling their inputs at the deep submicron 22nm technology node. HSPICE simulation using Berkeley Predictive technology models (BPTM) on different sizes and topologies of routing multiplexers show that the minimum leakage vector at the 22nm technology node significantly varies from that at 65nm node. This is due to higher gate leakage and output stage loading effects. The application of this vector results in 20% more leakage power saving as compared to the existing approaches. This technique saves significant leakage power because most of the routing multiplexers are unused in an FPGA. Moreover, there is no area overhead contrary to the existing approaches.
Starting Page	1129
Ending Page	1132
File Size	703251
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5117959
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Routing Multiplexing Energy consumption Batteries Circuits Threshold voltage Power engineering and energy Predictive models Topology
Content Type	Text
Resource Type	Article

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