NDLI: Optimization of structural adders in fixed coefficient transposed direct form FIR filters

Content Provider	IEEE Xplore Digital Library
Author	Faust, M. Chip-Hong Chang
Copyright Year	2009
Description	Author affiliation: Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore (Faust, M.; Chip-Hong Chang)
Abstract	Over the last two decades, fixed coefficient FIR filters were generally optimized by minimizing the number of adders required to implement the multiplier block in the transposed direct form filter structure. In this paper, an optimization method for the structural adders in the transposed tapped delay line is proposed. Although additional registers are required, an optimal trade-off can be made such that the overall combinational logic is reduced. For a majority of taps, the delay through the structural adder is shortened except for the last tap. The one full adder delay increase for the last optimized tap is tolerable as it does not fall in the critical path in most cases. The criterion for which area reduction is possible is analytically derived and an area reduction of up to 4.5% for the structural adder block of three benchmark filters is estimated theoretically. The saving is more prominent as the number of taps grows. Actual synthesis results obtained by Synopsys Design compiler with 0.18µm TSMC CMOS libraries show a total area reduction of up to 13.13% when combined with common subexpression elimination. In all examples, up to 11.96% of the total area saved were due to the reduction of structural adder costs by our proposed method.
Starting Page	2185
Ending Page	2188
File Size	708449
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5118230
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Costs Delay lines Application specific integrated circuits Embedded system Optimization methods Logic Added delay Estimation theory Libraries
Content Type	Text
Resource Type	Article

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