NDLI: A 140MS/s 10-bit pipelined ADC with a folded S/H stage

Content Provider	IEEE Xplore Digital Library
Author	Hwei-Yu Lee Shen-Iuan Liu
Copyright Year	2009
Description	Author affiliation: Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617, R.O.C. (Hwei-Yu Lee; Shen-Iuan Liu)
Abstract	A 140MS/s 10-bit pipelined analog-to-digital converter (ADC) using a folded sample-and-hold (S/H) stage and a 5-bit flash ADC is presented. To conquer the limited linear swing range results from an operational amplifier (OP-AMP). The proposed folded S/H stage allows the ADC to operate in the linear swing range of an OP-AMP. Only 17 comparators are required for a 5-bit flash ADC. Corresponding digital correction codes are added. The single-phase triggering method is adopted and it saves half the number of shift/latch elements. This pipelined ADC has been fabricated in a 0.18um CMOS process. It dissipates 65mW for a supply voltage of 1.8V. The measured signal-to-noise-plus-distortion ratio (SNDR) is achieved 55.4 dB. The differential nonlinearity (DNL) and integral nonlinearity (INL) is 0.78-LSB and 0.98-LSB, respectively.
Starting Page	976
Ending Page	979
File Size	818556
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5117921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Operational amplifiers Circuits Voltage Linearity Latches Logic CMOS process Calibration Sampling methods Switches
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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