NDLI: Exploring compiler optimizations for enhancing power gating

Content Provider	IEEE Xplore Digital Library
Author	Roy, S. Ranganathan, N. Katkoori, S.
Copyright Year	2009
Description	Author affiliation: Department of Computer Science and Engineering, University of South Florida, Tampa, 33620, USA (Roy, S.; Ranganathan, N.; Katkoori, S.)
Abstract	Power gating is a circuit level technique for reducing standby leakage in a circuit block by cutting off paths in it between the supply and the ground. A processor architecture that supports power gating of its resources may provide instructions that activate and deactivate those resources as part of the instruction set architecture level. Adequate compiler support is then required so that the power gating instructions can be inserted into the code to deactivate the resources that remain idle for long periods of time during program execution. However, the resource usage in a program depends on the code generated by the compiler. Thus, the code transformations performed by the compiler has an influence on the power gating opportunities of the processor resources. In this work, we explore target independent compiler optimizations that modify the functional unit usage in the loops of a procedure to enhance the opportunities to deactivate functional units in an embedded processor architecture. The optimizations performed on the code are sparse conditional constant propagation, lazy code motion, weak strength reduction, and operator strength reduction. Insertion of power gating instructions is performed by inspecting the idleness of the units in the regions enclosed within loops. We model the processor architecture with power gating support around an ARM core and use the SUIF framework for compiler support. Finally, we use the Simplescalar-ARM distribution to perform power and performance evaluation with a set of benchmarks from MiBench and MediaBench suites. Experimental results indicate that the integer multiplier in the processor core can be power gated for upto 99% of its idle cycles, for integer benchmarks, and upto 93%, for floating point benchmarks, when all the optimizations are performed. Moreover, the energy due to leakage in the functional units for the code with all the optimizations performed can be upto 51% lower, for integer benchmarks, and upto 21% lower, for floating point benchmarks, than that for the unoptimized code.
Starting Page	1004
Ending Page	1007
File Size	694101
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5117928
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optimizing compilers Circuits Program processors Very large scale integration Leakage current Microprocessors Sleep Computer science Power engineering and energy Computer architecture
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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