NDLI: Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-JPEG2000

Content Provider	IEEE Xplore Digital Library
Author	Wei-Ming Li Chih-Hsien Hsia Jen-Shiun Chiang
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, Tamkang University, Tamsui, Taipei, Taiwan (Wei-Ming Li; Chih-Hsien Hsia; Jen-Shiun Chiang)
Abstract	In this work, we propose a memory-efficient architecture of lifting based two-dimensional discrete wavelet transform (2-D DWT) for motion-JPEG2000. The proposed 2-D DWT architecture consists of a 1-D row processor, internal memory, and a 1-D column processor. The main advantage of this 2-D DWT is to reduce the internal memory requirement significantly. For an N×N image, only 2N and 4N sizes of internal memory are required for the 5/3 and 9/7 filters, respectively, to perform the one-level 2-D DWT decomposition. Moreover, it supports both lossless and lossy operation for 5/3 and 9/7 filters with high operation speed. The proposed 2-D DWT surpasses the existed lifting-based designs in the aspects of low internal memory requirement. It is suitable for VLSI implementation and can support various real-time image/video applications such as JPEG2000, motion-JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
Starting Page	750
Ending Page	753
File Size	994775
Page Count	4
File Format	PDF
ISBN	9781424438273
DOI	10.1109/ISCAS.2009.5117857
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-24
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Memory architecture Filters Convolutional codes Convolution Electronic mail Transform coding Image coding Two dimensional displays Very large scale integration
Content Type	Text
Resource Type	Article

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