NDLI: Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code

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Table of Contents

Message from the General Chair

Message from the Program Co-chairs

Special Panel Session

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling

FSimGP^2: An Efficient Fault Simulator with GPGPU

A Quasi-best Random Testing

Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits

On Determining the Real Output Xs by SAT-Based Reasoning

On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing

Design of DSP Virtual Machine Oriented All-Digital Simulation and Testing

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment

Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs

A Reliability Model for Object-Oriented Software

A New Approach to Generating High Quality Test Cases

A Study on Software Reliability Prediction Based on Transduction Inference

Formula-Oriented Compositional Minimization in Model Checking

Variation-Aware Fault Modeling

Diagnosis of Multiple Physical Defects Using Logic Fault Models

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

On Soft Error Immunity of Sequential Circuits

Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem

P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework

A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces

A Complete Logic BIST Technology with No Storage Requirement

Built-In Self-Test for Capacitive MEMS Using a Charge Control Technique

Defect Coverage-Driven Window-Based Test Compression

Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST

Parallel LFSR Reseeding with Selection Register for Mixed-Mode BIST

Efficient Embedding of Deterministic Test Data

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code

On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter

Pattern Encodability Enhancements for Test Stimulus Decompressors

High Performance Compaction for Test Responses with Many Unknowns

Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

D-Scale: A Scalable System-Level Dependable Method for MPSoCs

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits

XOR-Based Response Compactor Adaptive to X-Density Variation

DFT + DFD: An Integrated Method for Design for Testability and Diagnosability

Accelerating Strategy for Functional Test of NoC Communication Fabric

HYPERA: High-Yield Performance-Efficient Redundancy Analysis

A Comprehensive System-on-Chip Logic Diagnosis

On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking

Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure

At-speed Test of High-Speed DUT Using Built-Off Test Interface

Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated Stimulus

Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures

The Test Ability of an Adaptive Pulse Wave for ADC Testing

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation

Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

Seed Ordering and Selection for High Quality Delay Test

An Efficient Algorithm for Finding a Universal Set of Testable Long Paths

Distinguishing Resistive Small Delay Defects from Random Parameter Variations

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection

Thermal Safe High Level Test Synthesis for Hierarchical Testability

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit

On Bias in Transition Coverage of Test Sets for Path Delay Faults

Adaptive Low Shift Power Test Pattern Generator for Logic BIST

Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing

Modified Scan Flip-Flop for Low Power Testing

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power

A Test Integration Methodology for 3D Integrated Circuits

Application-Aware Online Testing for Many-Core SoC

Performance Characterization of TSV in 3D IC via Sensitivity Analysis

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation

Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing

New Microcode's Generation Technique for Programmable Memory Built-In Self Test

Software-Based Self-Testing of Processors Using Expanded Instructions

Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures

Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test

Test Cost Analysis for 3D Die-to-Wafer Stacking

Mining Complex Boolean Expressions for Sequential Equivalence Checking

On-the-Fly Reduction of Stimuli for Functional Verification

Test Time Analysis for IEEE P1687

Publisher's Information

2009 Asian Test Symposium

2008 17th Asian Test Symposium

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code

Content Provider	IEEE Xplore Digital Library
Author	Ishikawa, M. Yotsuyanagi, H. Hashizume, M.
Copyright Year	2010
Abstract	In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less conflicting bits with ATPG patterns when providing the test pattern to the scan chains. The experimental results show the method can reduce the test data volume than the previous method.
Starting Page	163
Ending Page	166
File Size	233003
Page Count	4
File Format	PDF
ISBN	9781424488414
ISSN	10817735
DOI	10.1109/ATS.2010.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters Automatic test pattern generation Circuit faults Built-in self-test Correlation Decoding scan chain ordering BIST-aided scan test test data reduction compatible flip-flops test pattern generation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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