NDLI: Post-CMOS parylene packaging for on-chip biosensor arrays

Content Provider	IEEE Xplore Digital Library
Author	Lin Li Mason, A.J.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, Michigan State University, East Lansing, USA (Lin Li; Mason, A.J.)
Abstract	The opportunity to integrate microfluidic devices with CMOS instrumentation is attractive to many biological and biomedical sensor applications. However, the packaging of CMOS circuitry for use within a liquid environment remains as an open challenge. This paper presents a robust and reliable packaging scheme for on-CMOS biosensors that is uniquely capable of providing both electrical insulation of a CMOS chip in a liquid environment and also protection from chemical and biological agents. In particular, this is the first reported CMOS packaging scheme capable of surviving harsh piranha solution that is needed to clean the surface of on-chip gold electrodes before final biointerface formation. The post-CMOS fabrication process is described for a $3×3mm^{2}$ CMOS die. Photos of a packaged CMOS biosensor array chip and electrochemical measurements in potassium ferrocyanide demonstrate proper operation of the device. The redox peak separation of on-chip electrodes was measured at 0.1V.
Starting Page	1613
Ending Page	1616
File Size	775907
Page Count	4
File Format	PDF
ISBN	9781424481705
ISSN	19300395
e-ISBN	9781424481699
e-ISBN	9781424481682
DOI	10.1109/ICSENS.2010.5690397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrodes CMOS integrated circuits Surface treatment Packaging Biosensors Fabrication Semiconductor device measurement
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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