NDLI: Binning optimization based on SSTA for transparently-latched circuits

Content Provider	IEEE Xplore Digital Library
Author	Min Gong Hai Zhou Jun Tao Xuan Zeng
Copyright Year	2009
Description	Author affiliation: State Key Lab of ASIC & System, Microelectronics Dept., Fudan University, China (Min Gong; Hai Zhou; Jun Tao; Xuan Zeng)
Abstract	With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation. Categories and Subject Descriptors: J.6 [Computer-Aided Engineering]: Computer-Aided Design General Terms: Design, Algorithms
Starting Page	328
Ending Page	335
File Size	346399
Page Count	8
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Circuit testing Cost function Clocks Microprocessors Latches Distributed computing Grid computing Stochastic processes Greedy algorithms Marketing and sales Latched Circuits Binning Optimization SSTA
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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