NDLI: Mitigation of intra-array SRAM variability using adaptive voltage architecture

Content Provider	IEEE Xplore Digital Library
Author	Singh, A.K. Ku He Caramanis, C. Orshansky, M.
Copyright Year	2009
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA (Singh, A.K.; Ku He; Caramanis, C.; Orshansky, M.)
Abstract	SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These constraints determine both the minimum cell size and supply voltage. RCM is set by the maximum read access time over the array. The randomness of transistor threshold voltages, and thus read times, makes maximum read time follow extreme order statistics, specifically, the Gumbel distribution which is characterized by long tails. Thus, the margin specification needs to be met at the high sigma corners in order to reach acceptable yield, resulting in oversizing and increased VDD. In this work, we demonstrate that a reduced-area bitcell design is achievable by reducing the impact of intra-array randomness through a new architecture that employs an adaptive voltage scheme in a partitioned SRAM array. The key idea is to be able to shift empirical distributions (realizations) of read time in a set of rows that form a single partition to meet the target. Because the partition is smaller than the whole array, the tail of the Gumbel distribution is significantly reduced. The adaptive voltage tuning policy is driven by the worst partition access time. For the blocks whose delay violates access time constraints, a higher voltage is selected out of the available set to gain yield, otherwise voltage is reduced for power saving. This permits smaller cell area and lower $V_{DD}$ at identical yield. The cost of adaptivity is in generation and routing of a small number (in our experiments, four) voltage levels and the area of one-per-partition set of PMOS switches. We demonstrate that through the voltage tuning architecture we propose, it is possible to obtain mean power consumption reduction on average by 21% iso-area. Alternatively, bitcell area can be reduced on average by 7% iso-power compared to the existing design strategy.
Starting Page	637
Ending Page	644
File Size	342557
Page Count	8
File Format	PDF
ISBN	9781605588001
ISSN	10923152
DOI	10.1145/1687399.1687517
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Random access memory Probability distribution Energy efficiency Threshold voltage Statistical distributions Adaptive arrays Delay effects Time factors Costs Routing
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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