NDLI: An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis

Content Provider	IEEE Xplore Digital Library
Author	Zuochang Ye Zhiping Yu
Copyright Year	2009
Description	Author affiliation: Tsinghua University (Zuochang Ye; Zhiping Yu)
Abstract	Statistical full-chip leakage analysis considering spatial correlation is highly expensive due to its $O(N^{2})$ complexity for logic circuits with N gates. Although efforts have been made to reduce the cost at the loss of accuracy, existing methods are still unsuitable for large-scale problems. In this paper we resolve the problem by re-formulating the computation to one that can be done efficiently using a well-developed technique that has been widely used in fast EM simulation and machine learning areas. The resulting algorithm is provably of O(N) or O(N log N) complexity with well-defined and easily-controlled error bounds. Experiments show that using the proposed method it is feasible to handle million-gate circuits within only a few minutes on a regular desktop PC. The corresponding error is less than 0.5% compared to exhausted computation that takes more than 3 days. The proposed method is about 300X faster and 10X more accurate compared to existing grid-approximation method.
Starting Page	295
Ending Page	301
File Size	213857
Page Count	7
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Algorithm design and analysis Leakage current Costs Large-scale systems Computational modeling Machine learning Logic circuits Spatial resolution Circuit simulation Machine learning algorithms
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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