NDLI: POWER7 — Verification challenge of a multi-core processor

Content Provider	IEEE Xplore Digital Library
Author	Schubert, K.-D.
Copyright Year	2009
Description	Author affiliation: IBM Deutschland, Research & Development GmbH, Schönaicher Str. 220, D-71032 Böblingen (Schubert, K.-D.)
Abstract	Over the years functional hardware verification has made significant progress in the areas of traditional simulation techniques, hardware accelerator usage and last but not least formal verification approaches. This has been sufficient to deal with the additional design content and complexity increase that has been happening at the same time. For POWER7, IBM's first high end 8-core microprocessor, these incremental improvements in verification have been deemed not to be enough by themselves, because the chip was not just a remap of an existing design with more cores. The infrastructure on the chip had to be changed significantly, while at the same time the business side requested a shorter development cycle with perfect quality but without growing the team. Looking at these constraints a two phase approach seemed to be the only solution. This paper commences with the highlights of the first phase, where improvements to the existing process have been identified. This includes topics ranging from enhanced test case generation, over advancements in structural checking to the extensions of the formal verification scope both in property checking and sequential equivalence checking. At the same time, the paper describes the second phase which has targeted the exploitation of synergy across the various verification activities. The active interlock between simulation, formal verification and the design has helped to reduce workload and improved the project schedule. And the usage of coverage in holistic way from unit level simulation to acceleration has led to new innovations and new insight, which improved the overall verification process. Finally, an outlook on future challenges and future trends is given. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids — Verification. General Terms Verification
Starting Page	809
Ending Page	812
File Size	219324
Page Count	4
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Multicore processing Testing Hardware Formal verification Microprocessors Life estimation Energy management Permission Yarn Sequential analysis Structural Checking Simulation Formal Verification Hardware Acceleration Test Generation
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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