NDLI: GRPlacer: Improving routability and wire-length of global routing with circuit replacement

Content Provider	IEEE Xplore Digital Library
Author	Ke-Ren Dai Chien-Hung Lu Yih-Lang Li
Copyright Year	2009
Description	Author affiliation: Department of Computer Science National Chiao Tung University (Ke-Ren Dai; Yih-Lang Li) \|\| Springsoft Inc. (Chien-Hung Lu)
Abstract	Placement profoundly impacts physical design owing to its role in determining the lower bound of a circuit wirelength, as well as the circuit routability. To close the gap between placement and routing, this study integrates global routing and placement to improve the wirelength estimation accuracy of placement. Two methods, called wirelength-reduced cell shifting and cell rearrangement by bipartite matching, are applied to minimize wirelength. Cell sorting based congestion reduction and pattern-prerouting based congestion-avoided cell shifting are proposed to reduce congestion. Experimental results demonstrate that the proposed placer improves total routed wirelength by 2% to ROOSTER on IBMv2 benchmarks. Moreover, the proposed GRPlacer resolves the original congested regions of the placements generated by ROOSTER. Compare with the detailed placer in ROOSTER, our work can reduce more routed wire length and remove more overflows.
Starting Page	351
Ending Page	356
File Size	269186
Page Count	6
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Routing Circuits Minimization Computer science Sorting Wire White spaces Very large scale integration Delay Pins
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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GRPlacer: improving routability and wire-length of global routing with circuit replacement

Optimal redistribution of white space for wire length minimization

Guiding global placement with wire density

Unconstrained via minimization for topological multilayer routing

Track assignment: a desirable intermediate step between global routing and detailed routing

FastRoute: A Step to Integrate Global Routing into Placement

Congestion minimization during placement without estimation

An efficient hierarchical timing-driven Steiner tree algorithm for global routing

A signed hypergraph model of constrained via minimization

GRPlacer: Improving routability and wire-length of global routing with circuit replacement

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GRPlacer: improving routability and wire-length of global routing with circuit replacement

Optimal redistribution of white space for wire length minimization

Guiding global placement with wire density

Unconstrained via minimization for topological multilayer routing

Track assignment: a desirable intermediate step between global routing and detailed routing

FastRoute: A Step to Integrate Global Routing into Placement

Congestion minimization during placement without estimation

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A signed hypergraph model of constrained via minimization

GRPlacer: Improving routability and wire-length of global routing with circuit replacement