NDLI: IPR: In-Place Reconfiguration for FPGA fault tolerance

Content Provider	IEEE Xplore Digital Library
Author	Zhe Feng Yu Hu Lei He Majumdar, R.
Copyright Year	2009
Description	Author affiliation: Computer Science Department University of California, Los Angeles (Majumdar, R.) \|\| Electrical Engineering Department (Zhe Feng; Yu Hu; Lei He)
Abstract	We describe In-Place Reconfiguration (IPR) for LUT-based FPGAs, an algorithm that maximizes identical configuration bits for complementary inputs of a LUT thereby reducing the propagation of faults seen at a pair of complementary inputs. Based on IPR, we develop a fault-tolerant logic resynthesis algorithm which decreases the circuit fault rate while preserving functionality and topology of the LUT-based logic network. Since the topology is preserved, the resynthesis algorithm can be applied post-layout and without changes in physical design. Compared to the state-of-the-art academic technology mapper Berkeley ABC, IPR reduces the relative fault rate by 48% and increases MTTF by 1.94× with the same area and performance, and IPR combined with a previous fault-tolerant logic resynthesis algorithm (ROSE) reduces the relative fault rate by 49% and increases MTTF by 2.40× with 19% less area but same performance. The above improvement assumes a stochastic single fault and more improvement is expected for multi-fault models.
Starting Page	105
Ending Page	108
File Size	200557
Page Count	4
File Format	PDF
ISBN	9781605588001
ISSN	10923152
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Intellectual property Field programmable gate arrays Fault tolerance Circuit faults Logic circuits Network topology Circuit topology Table lookup Reconfigurable logic Algorithm design and analysis
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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IPR: In-Place Reconfiguration for FPGA fault tolerance

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