NDLI: Combination of Fine Pitch and High Uniformity of Lead-Free Plating-Based Flip Chip Solder Bumps

Content Provider	IEEE Xplore Digital Library
Author	Jung-Tang Huang Pen-Shan Chao Hou-Jun Hsu Sheng-Hsiung Shih
Copyright Year	2006
Description	Author affiliation: Nat. Taipei Univ. of Technol., Taipei (Jung-Tang Huang; Pen-Shan Chao; Hou-Jun Hsu; Sheng-Hsiung Shih)
Abstract	Electroplating is by far the most promising process to fabricate fine pitch solder bumps in flip chip. However, rugged surface and poor coplanarity resulted from numerous variable plating parameters generally cause short circuit and broken circuit to affect packaging reliability. With the great demand for decreasing pitch size below 100 um, solder bumps' coplanarity would become more and more important as considering alignment in advanced three-dimensional packaging and WLP (Wafer Level Packaging). This paper aims to provide a creative solder bump fabrication process that is characterized by using a polishing mechanism to transform the plated solder bumps with huge height deviation into smooth and uniform ones. Predominately in mechanical polishing force enables it to polish much wider height deviation, typically affected by poor current distribution in tiny area plating. Equipped with a specific soft non-woven polishing pad and a self-designed substrate holder, the polisher features large MRR (Material Removal Rate), easy manipulation and high efficiency. The final experimental results indicate that the polishing rate in lead-free Sn-Cu solder bumps could reach as fast as 4~5 um/min, almost 50 times faster than CMP (Chemical Mechanical Polishing). The whole coplanarity of solder bumps at 80 um pitch size could be sharply decreased from 33plusmn2.5 um (7.5%) after plating to 28plusmn1 um (3%) after polishing and even 26plusmn0.5 um (1%) after re flow. Most importantly, each single die (6 mmtimes6 mm) after re flow could be controlled as accurately as within 0.5%. This proposed polishing mechanism could assist the plating-based solder bumps in precisely getting better coplanarity so as to enhance packaging reliability and yield.
Starting Page	1
Ending Page	6
File Size	2333015
Page Count	6
File Format	PDF
ISBN	9781424408337
DOI	10.1109/EMAP.2006.4430613
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Environmentally friendly manufacturing techniques Lead Flip chip Circuits Wafer scale integration Electronics packaging Current density Chemicals Costs Fixtures
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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