NDLI: Residual Stress Distribution in Stacked LSI Chips Mounted by Flip Chip Technology

Content Provider	IEEE Xplore Digital Library
Author	Ueta, N. Miura, H.
Copyright Year	2006
Description	Author affiliation: Tohoku Univ., Sendai (Ueta, N.; Miura, H.)
Abstract	Since mechanical stress affects both electronic functions and reliability of LSI chips, it has become strongly important to minimize the residual stress in LSI chips. This is because the residual stress increases significantly by changing the bonding structure between an LSI chip and a substrate from a wire-bonding structure (WB) to a flip-chip structure (FC). A finite element analysis, therefore, was performed to make clear the quantitative residual stress distribution in stacked chips mounted by flip chip technology using area-arrayed metallic bumps. The maximum value of the normal stress on a transistor formation surface of a chip shifts about -200 MPa by changing the assembly structure from WB to FC. A periodic distribution with amplitude of about 90 MPa also appears due to the periodic alignment of the metallic bumps. Such a change of the residual stress in an LSI chip causes a shift of electronic functions of semiconductor devices in a local area of the chip. The important structural factors that determine the distribution of the residual stress are found to be the thickness of a chip, the height of a bump, the width of a bump, the period of the bumps, and the thermal expansion coefficient of underfill material. The average residual stress in the stacked two chips varies depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps in an upper connection layer and a bottom connection layer. Therefore, it is very important to optimize the thickness of a chip, the position (layout) of bumps, and other structural factors to minimize not only the average residual stress but also the amplitude of the periodic stress distribution. Finally, the estimated stress distribution was proved in detail by experiments using stress-sensing chips with 10-mum long gauges.
Starting Page	1
Ending Page	6
File Size	2996618
Page Count	6
File Format	PDF
ISBN	9781424408337
DOI	10.1109/EMAP.2006.4430593
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Residual stresses Large scale integration Flip chip Bonding Substrates Finite element methods Performance analysis Assembly Periodic structures Semiconductor devices
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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