NDLI: Industry Drop Tests in Solder Joint Reliability Study of Molded Flip Chip Package

Content Provider	IEEE Xplore Digital Library
Author	Kang Eu Ong Wei Kea Loh Chee Wai Wong Yeen San Yip Choi Keng Chan Lim, S.A. Seok Ling Lee Ganapathysubramanian, S.
Copyright Year	2006
Description	Author affiliation: Intel Technol. Sdn Bhd, Kulim (Kang Eu Ong; Wei Kea Loh; Chee Wai Wong; Yeen San Yip; Choi Keng Chan; Lim, S.A.; Seok Ling Lee)
Abstract	In this paper, the author has compared the package performance of molded flip chip package in two types of industry drop test conditions namely test J and N. Drop dynamic analysis, failure mechanism and board design options were discussed in detail. High speed camera (HSC) and strain measurement analyses were used in this study. It was found that the molded package has a shorter life span when tested using drop test J as compared to drop test N; even though test N has a higher shock pulse than test J. From HSC data and strain measurement, higher board deflection and board strain were observed in test J condition. This suggested that strain metric is the key factor to determine the solder joint reliability and not the shock pulse. Further analysis with failure analysis (FA) revealed that the major failure mode at solder joint package interface is mechanical fatigue crack while at the board side is dominated by brittle fracture crack and broken board trace. Broken board trace failure was identified as the key factor which attributed to lower drop performance. Dependency of drop performance to different board pad designs such as via-off-pad (VoP) and via-in-pad (ViP) were considered. The experiment was also complemented with detail finite element analysis (FEA) to establish design sensitivity in molded flip chip package; such as recommendation of a better board trace routing design. In summary, the study found that drop test J is more stringent than drop test N and optimizing the board trace design can improve the solder joint reliability (SJR).
Starting Page	1
Ending Page	7
File Size	3230519
Page Count	7
File Format	PDF
ISBN	9781424408337
DOI	10.1109/EMAP.2006.4430610
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Soldering Flip chip Packaging Life testing Failure analysis Strain measurement Electric shock Performance analysis Cameras Pulse measurements
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Solder Joint Reliability Performance of Flip Chip Molded Ball Grid Array (BGA) Package for Network/Communication Application

Flip chip advanced package solder joint embrittlement fault isolation using TDR

Solder joint attachment reliability evaluation and failure analysis of the 244 I/O pre-molded PolyHIC package

New failure mode induced by electric current in flip chip solder joint

Influence of Package Assembly Process on Solder Joint Reliability - an Application of Component Level Shock Methodology

Package to board interconnection shear strength (PBISS) behavior at high strain rates approaching mechanical drop

Solder Joint Reliability of BGA Package under End-User Handling Test Conditions

Lead-free 96.5Sn-3.5Ag flip chip solder joint reliability analysis

Correlating Circuit Board Deflection/Strain Measurements to BGA Solder Joint Dynamic Performance

Industry Drop Tests in Solder Joint Reliability Study of Molded Flip Chip Package

Similar Documents

Solder Joint Reliability Performance of Flip Chip Molded Ball Grid Array (BGA) Package for Network/Communication Application

Flip chip advanced package solder joint embrittlement fault isolation using TDR

Solder joint attachment reliability evaluation and failure analysis of the 244 I/O pre-molded PolyHIC package

New failure mode induced by electric current in flip chip solder joint

Influence of Package Assembly Process on Solder Joint Reliability - an Application of Component Level Shock Methodology

Package to board interconnection shear strength (PBISS) behavior at high strain rates approaching mechanical drop

Solder Joint Reliability of BGA Package under End-User Handling Test Conditions

Lead-free 96.5Sn-3.5Ag flip chip solder joint reliability analysis

Correlating Circuit Board Deflection/Strain Measurements to BGA Solder Joint Dynamic Performance

Industry Drop Tests in Solder Joint Reliability Study of Molded Flip Chip Package