NDLI: A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Siozios, K. Pavlidis, V.F. Soudris, D.
Copyright Year	2009
Description	Author affiliation: School of Electrical and Computer Engineering, National Technical University of Athens, Greece (Siozios, K.; Soudris, D.) \|\| LSI-EPFL, 1015 Lausanne, Switzerland (Pavlidis, V.F.)
Abstract	Interconnect structures significantly contribute to the delay, power consumption, and silicon area of modern reconfigurable architectures. The demand for higher clock frequencies and logic densities is also important for the Field-Programmable Gate Array (FPGA) paradigm. Three-dimensional (3-D) integration can alleviate such performance limitations by accommodating a number of additional silicon layers. However, the benefits of 3-D integration have yet to be sufficiently investigated. In this paper, we propose a software-supported methodology to explore and evaluate 3-D FPGAs fabricated with alternative technologies. Based on the evaluation results, the proposed FPGA device improves speed and energy dissipation by approximately 38% and 26%, respectively, as compared to 2-D FPGAs. Furthermore, these gains are achieved in addition to reducing the interlayer connections, as compared to existing design approaches, leading to cheaper and more reliable architectures.
Starting Page	172
Ending Page	177
File Size	768190
Page Count	6
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Field programmable gate arrays Silicon Logic arrays Delay Energy consumption Reconfigurable architectures Clocks Frequency Reconfigurable logic Energy dissipation CAD tools FPGA 3-D integration interconnection architectures
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

Reconfigurable Asynchronous Logic

Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs

Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs

Low Power Consumption Coarse Grained Reconfigurable Adder

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs

Similar Documents

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

Reconfigurable Asynchronous Logic

Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

A Novel Methodology for Exploring Interconnection Architectures Targeting 3-D FPGAs

Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs

Low Power Consumption Coarse Grained Reconfigurable Adder

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs