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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Li Jiang Lin Huang Qiang Xu |
| Copyright Year | 2009 |
| Description | Author affiliation: CUhk REliable computing laboratory (CURE), Department of Computer Science & Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong (Li Jiang; Lin Huang; Qiang Xu) |
| Abstract | Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such giga-scale integrated circuits. In this paper, we propose novel test solutions for 3D SoCs manufactured with die-to-wafer and die-to-die bonding techniques. Both testing time and routing cost associated with the test access mechanisms in 3D SoCs are considered in our simulated annealing-based technique. Experimental results on ITC'02 SoC benchmark circuits are compared to those obtained with two baseline solutions, which show the effectiveness of the proposed technique. |
| Starting Page | 220 |
| Ending Page | 225 |
| File Size | 137615 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Design optimization Circuit testing System-on-a-chip Integrated circuit technology Integrated circuit testing Integrated circuit manufacture Cost function Pulp manufacturing Bonding Routing |
| Content Type | Text |
| Resource Type | Article |
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