NDLI: A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Content Provider	IEEE Xplore Digital Library
Author	Nagaraj, K. Kundu, S.
Copyright Year	2009
Description	Author affiliation: University of Massachusetts, Amherst, USA (Nagaraj, K.; Kundu, S.)
Abstract	Optical shrink for process migration, manufacturing process variation, temperature and voltage changes lead to clock skew as well as path delay variations in a manufactured chip. Such variations end up degrading the performance of manufactured chips. Since, such variations are hard to predict in pre-silicon phase, tunable clock buffers have been used in several designs. These buffers are tuned to improve maximum operating clock frequency of a design. Previously, we have presented an algorithmic approach that uses delay measurements on a few selected patterns to determine which buffers should be targeted for tuning. In this paper, a study on impact of tunable buffer placement on performance is reported. Greatest benefit from tunable buffer placement is observed, when the clock tree is designed by the proposed tuning system assuming random delay perturbations during design. Accordingly, we present a clock tree synthesis procedure which offer very good protection against process variation as borne out by the results.
Starting Page	292
Ending Page	295
File Size	99750
Page Count	4
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Silicon Clocks Optical buffering Manufacturing processes Delay Optical tuning Temperature Voltage Degradation Frequency
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements

Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks

Variation Aware Design of Post-Silicon Tunable Clock Buffer

A New Algorithm for Post-Silicon Clock Measurement and Tuning

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency

Process variation mitigation via post silicon clock tuning

TuneLogic: Post-silicon tuning of dual-Vdd designs

TuneFPGA: Post-silicon tuning of dual-Vdd FPGAs

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Similar Documents

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements

Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks

Variation Aware Design of Post-Silicon Tunable Clock Buffer

A New Algorithm for Post-Silicon Clock Measurement and Tuning

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency

Process variation mitigation via post silicon clock tuning

TuneLogic: Post-silicon tuning of dual-Vdd designs

TuneFPGA: Post-silicon tuning of dual-Vdd FPGAs

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation