NDLI: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

Content Provider	IEEE Xplore Digital Library
Author	Seiculescu, C. Murali, S. Benini, L. De Micheli, G.
Copyright Year	2009
Description	Author affiliation: DEIS, Univerity of Bologna, Italy (Benini, L.) \|\| LSI, EPFL, Lausanne, Switzerland (Seiculescu, C.; De Micheli, G.) \|\| iNoCs, Lausanne, Switzerland (Murali, S.)
Abstract	Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.
Starting Page	9
Ending Page	14
File Size	249434
Page Count	6
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Network-on-a-chip Network topology Network synthesis System-on-a-chip Integrated circuit interconnections Delay Circuit topology Integrated circuit synthesis Three-dimensional integrated circuits Integrated circuit technology placement 3D ICs Networks on chip (NoC) synthesis topology
Content Type	Text
Resource Type	Article

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