NDLI: Cache aware compression for processor debug support

Content Provider	IEEE Xplore Digital Library
Author	Vishnoi, A. Panda, P.R. Balakrishnan, M.
Copyright Year	2009
Description	Author affiliation: Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016, India (Vishnoi, A.; Panda, P.R.; Balakrishnan, M.)
Abstract	During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, the bulk of which is composed of cache, the problem is essentially that of transferring cache contents off-chip, to a logic analyzer. In order to reduce the transfer time and save expensive logic analyzer memory, we propose to compress the cache contents on their way out. We present a hardware compression engine for cache data using a Cache Aware Compression strategy that exploits knowledge of the cache fields and their behavior to achieve an effective compression. Experimental results indicate that the technique results in 7–31% better compression than one that treats the data as just one long bit stream. We also describe and evaluate a parallel compression architecture that uses multiple compression engines, resulting in a 54% reduction in transfer time.
Starting Page	208
Ending Page	213
File Size	178246
Page Count	6
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Hardware Engines Logic testing Debugging Delay Computer science Costs Data compression Silicon Test data compression
Content Type	Text
Resource Type	Article

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