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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | van Moll, H.W.M. Corporaal, H. Reyes, V. Boonen, M. |
| Copyright Year | 2009 |
| Description | Author affiliation: Technical University Eindhoven, The Netherlands (van Moll, H.W.M.; Corporaal, H.) || NXP Semiconductors, Eindhoven, The Netherlands (Reyes, V.; Boonen, M.) |
| Abstract | The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These models need to be functional and timing accurate in order to address different design use-cases during the SoC development. However the typical issue with Transaction Level Modeling (TLM) techniques is the accuracy vs. simulation speed trade-off. Models that can run at high simulation speeds are often modeled at abstraction levels that make them unsuitable for use-cases where timing accuracy is required. Similarly, most models that are cycle accurate are inherently too slow (due to clock sensitive processes) to be used in use-cases where high simulation speed is key. This paper introduces a new methodology that enables the creation of fast and cycle accurate protocol specific bus-based communication models, based on the new TLM 2.0 standard from the Open SystemC Initiative (OSCI). |
| Starting Page | 316 |
| Ending Page | 319 |
| File Size | 479094 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Protocols Timing Accuracy Clocks Communication standards Virtual prototyping Electronic design automation and methodology Time to market Pipeline processing Payloads |
| Content Type | Text |
| Resource Type | Article |
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