NDLI: A highly resilient routing algorithm for fault-tolerant NoCs

Content Provider	IEEE Xplore Digital Library
Author	Fick, D. DeOrio, A. Chen, G. Bertacco, V. Sylvester, D. Blaauw, D.
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 48109, USA (Fick, D.; DeOrio, A.; Chen, G.; Bertacco, V.; Sylvester, D.; Blaauw, D.)
Abstract	Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as systems on a chip (SoC) and chip multiprocessor (CMP) designs, where even a single device failure can cause fatal system errors. Resiliency to device failure will be a necessary condition at future technology nodes. In this work, we present a network-on-chip (NoC) routing algorithm to boost the robustness in interconnect networks, by reconfiguring them to avoid faulty components while maintaining connectivity and correct operation. This distributed algorithm can be implemented in hardware with less than 300 gates per network router. Experimental results over a broad range of 2D-mesh and 2D-torus networks demonstrate 99.99% reliability on average when 10% of the interconnect links have failed.
Starting Page	21
Ending Page	26
File Size	251430
Page Count	6
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Routing Fault tolerance Network-on-a-chip Hardware System-on-a-chip Maintenance Joining processes Fault tolerant systems Monte Carlo methods Computer network reliability
Content Type	Text
Resource Type	Article

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