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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sahu, A. Balakrishnan, M. Panda, P.R. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of Computer Science and Engineering, Indian Institute of Technology Delhi, Hauz Khas, New Delhi, India, 110016 (Sahu, A.; Balakrishnan, M.; Panda, P.R.) |
| Abstract | This paper deals with a methodology for software estimation to enable design space exploration of heterogeneous multiprocessor systems. Starting from fork-join representation of application specification along with high level description of multiprocessor target architecture and mapping of application components onto architecture resource elements, it estimates the performance of application on target multiprocessor architecture. The methodology proposed includes the effect of basic compiler optimizations, integrates light weight memory simulation and instruction mapping for complex instruction to improve the accuracy of software estimation. To estimate performance degradation due to contention for shared resources like memory and bus, synthetic access traces coupled with interval analysis technique is employed. The methodology has been validated on a real heterogeneous platform. Results show that using estimation it is possible to predict performance with average errors of around 11%. |
| Starting Page | 1018 |
| Ending Page | 1023 |
| File Size | 173086 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Delay estimation Application software Computer architecture Space technology Space exploration Software performance Optimizing compilers Computer science Design engineering Paper technology |
| Content Type | Text |
| Resource Type | Article |
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