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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Huynh, H.P. Mitra, T. |
| Copyright Year | 2009 |
| Description | Author affiliation: School of Computing, National University of Singapore (Huynh, H.P.; Mitra, T.) |
| Abstract | This paper explores runtime reconfiguration of custom instructions in the context of multi-tasking real-time embedded systems. We propose a pseudo-polynomial time algorithm that minimizes processor utilization through customization and runtime reconfiguration, while satisfying all the timing constraints. Our experimental infrastructure consists of Stretch customizable processor supporting runtime reconfiguration as the hardware platform and realistic embedded benchmarks as applications. We observe that runtime reconfiguration of custom instructions can help to reduce the processor utilization by up to 64%. The experimental results also demonstrate that our algorithm is highly scalable and achieves optimal or near optimal (3% difference) processor utilization. |
| Starting Page | 1536 |
| Ending Page | 1541 |
| File Size | 268079 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Runtime Real time systems Embedded system Hardware Fabrics Timing Computer aided instruction Processor scheduling Energy consumption Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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