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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Siozios, K. Sotiriadis, K. Pavlidis, V.F. Sondris, D. |
| Copyright Year | 2007 |
| Description | Author affiliation: Democritus Univ. of Thrace, Thrace (Siozios, K.; Sotiriadis, K.) |
| Abstract | This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPR0 for placement and routing on 3D FPGAs and (ii) the 3DPower for power/energy estimation on such architectures. We mainly focus our exploration on the total number of layers and the amount of vertical interconnects (or vias). The efficiency of the proposed architecture is evaluated by making an exhaustive exploration for via connections under the Energy x Delay Product criterion. Experimental results demonstrate the effectiveness of our solution, considering the 20 largest MCNC benchmarks. Considering 3D architectures with 4 layers and two scenarios of fabricated via densities (30% and 70%), we achieve an average decrease in the delay, the wire length, and the energy consumption of 18%, 17%, and 31%, respectively, as compared to 2D FPGAs. We also achieved high utilization of vias links. |
| Starting Page | 652 |
| Ending Page | 655 |
| File Size | 5535728 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424410590 |
| DOI | 10.1109/FPL.2007.4380738 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-08-27 |
| Publisher Place | Netherlands |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Design methodology Design automation Energy consumption Wire Delay Routing Integrated circuit interconnections Switches Manufacturing industries |
| Content Type | Text |
| Resource Type | Article |
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