NDLI: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique

Content Provider	IEEE Xplore Digital Library
Author	Siozios, K. Soudris, D. Thanailakis, A.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi (Siozios, K.; Soudris, D.; Thanailakis, A.)
Abstract	Power consumption is one of the major headaches, which should be tackled by the designers. Also, the parameters that affect significantly the performance and power are the configurable logic blocks (CLBs) and the interconnection components. A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The main goal of this technique is to spread out the power consumption across the whole device, as well as to minimize it, achieving a more uniform power consumption map across the whole FPGA. This approach is based on finding the optimal CLB placement according to resource utilization map. The proposed methodology can be applied for mapping applications with an efficient power management strategy. Furthermore, the proposed placement algorithm reduces the total power consumption, the leakage power, the total energy and silicon area. The proposed methodology is fully-supported by the software tool called EX-VPR. The result of applying this placement strategy is the power consumption reduction about 5%, while we distribute the power consumption with a rather "uniformly" fashion across the whole device minimizing the power spikes
Starting Page	204
Ending Page	209
File Size	644023
Page Count	6
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313234
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Energy consumption Reconfigurable logic Silicon Reconfigurable architectures Resource management Application software Energy management Software tools Field programmable gate arrays Logic devices
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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