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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Holcomb, D. Wenchao Li Seshia, S.A. |
| Copyright Year | 2009 |
| Description | Author affiliation: EECS Department, UC Berkeley, USA (Holcomb, D.; Wenchao Li; Seshia, S.A.) |
| Abstract | Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardening have been proposed to synthesize circuits that are tolerant to soft errors. However, each such technique has associated overheads of power, area, and performance. In this paper, we present a new methodology to compute the failures in time (FIT) rate of a sequential circuit where the failures are at the system-level. System-level failures are detected by monitors derived from functional specifications. Our approach includes efficient methods to compute the FIT rate of combinational circuits (CFIT), incorporating effects of logical, timing, and electrical masking. The contribution of circuit components to the FIT rate of the overall circuit can be computed from the CFIT and probabilities of system-level failure due to soft errors in those elements. Designers can use this information to perform Pareto-optimal hardening of selected sequential and combinational components against soft errors. We present experimental results demonstrating that our analysis is efficient, accurate, and provides data that can be used to synthesize a low-overhead, low-FIT sequential circuit. |
| Starting Page | 785 |
| Ending Page | 790 |
| File Size | 453318 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Error analysis Sequential circuits Latches Combinational circuits Computer errors Circuit simulation Circuit synthesis Timing Logic Digital circuits |
| Content Type | Text |
| Resource Type | Article |
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