NDLI: Group-caching for NoC based multicore cache coherent systems

Content Provider	IEEE Xplore Digital Library
Author	Wang Zuo Shi Feng Zuo Qi Ji Weixing Li Jiaxin Deng Ning Xue Licheng Tan Yuan Qiao Baojun
Copyright Year	2009
Description	Author affiliation: High Performance Embedded Computation Lab, School of Computer Science and Technology, Beijing Institute of Technology, China (Wang Zuo; Shi Feng; Zuo Qi; Ji Weixing; Li Jiaxin; Deng Ning; Xue Licheng; Tan Yuan; Qiao Baojun)
Abstract	Most CMPs use on-chip networks to connect cores and tend to integrate more simple cores on a single die. Low-radix networks, such as 2D-MESH, are widely used in tiled CMPs since they can be mapped to on-chip networks efficiently. However, low-radix networks introduce high network latency caused by long diameter. In this paper, we propose the use of group-caching design in NoC based multicore cache coherent systems. In our design, on-chip L2 banks are organized to form multiple groups. Each cache group behaves like a shared L2 cache for the cores inside cache group while the cache coherence between cache groups is maintained by coherence messages. Besides, group-caching also adopts the new cache replacement policy to improve the inefficient use of the aggregate L2 cache capacity. Compared to banked and shared L2 design, as most L2 accesses are served by local cache group, the hop count is significantly reduced. Experiment results based on full-system simulation show that for 2D-MESH, group-caching can increase the performance by 2%∼8% compared to banked and shared L2 design, with network energy consumption reduced by 11%∼13%. Experiment results also show that the communication overhead inside cache group plays an important role in the performance of groupcaching.
Starting Page	755
Ending Page	760
File Size	284752
Page Count	6
File Format	PDF
ISBN	9781424437818
ISSN	15301591
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Network-on-a-chip Multicore processing Delay System-on-a-chip Aggregates Network topology Wires Telecommunication traffic Traffic control Computer networks power CMP NOC network latency L2 banks cache coherence group-caching performance
Content Type	Text
Resource Type	Article

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