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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Milder, P.A. Hoe, J.C. Puschel, M. |
| Copyright Year | 2009 |
| Description | Author affiliation: Carnegie Mellon University, Electrical and Computer Engineering Department, Pittsburgh, PA, U.S.A. (Milder, P.A.; Hoe, J.C.; Puschel, M.) |
| Abstract | This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points streamed at a rate of w per cycle, performs a permutation over all n points, and outputs the result in the same streaming format. We describe the system and its requirements mathematically and use this mathematical description to show that the datapaths resulting from our technique can sustain a full throughput of w words per cycle without stalling. Additionally, we provide an algorithm to configure the datapath for a given permutation and streaming width. Using this technique, we have constructed a full synthesis system that takes as input a permutation and a streaming width and outputs a register-transfer level Verilog description of the datapath. We present an evaluation of our generated designs over varying problem sizes and streaming widths, synthesized for a Xilinx Virtex-5 FPGA. |
| Starting Page | 1118 |
| Ending Page | 1123 |
| File Size | 200683 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424437818 |
| ISSN | 15301591 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-04-20 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | European Design Automation Association (EDAA) |
| Subject Keyword | Throughput Random access memory Data engineering Computer architecture Hardware design languages Field programmable gate arrays Wires Information retrieval Design methodology |
| Content Type | Text |
| Resource Type | Article |
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