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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Peng Liu Huibiao Zhu Naiyong Jin |
| Copyright Year | 2012 |
| Description | Author affiliation: Verification Group, Synopsys Inc., Shanghai (Naiyong Jin) || Software Engineering Institute, East China Normal University, China (Peng Liu; Huibiao Zhu) |
| Abstract | In Verilog programs, multiple non blocking assignments (NBA) to the same signal in an identical always structure may introduce conflicts and nondeterministic behaviors. It is a severe design flaw. In this paper, we propose a control flow graph based symbolic approach for detecting conflicts caused by non blocking assignments. This approach applies the static analysis method on the parallel nature of Verilog programs, and adopts the Multi-valued Decision Diagram (MDD) to symbolically encode the reachability conditions with flexibility and efficiency. Our static analysis approach shows valid results from our tests. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 486030 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6467951 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware design languages Boolean functions Data structures Indexes Encoding Flow graphs Software engineering Conflict Detection Static Verification Symbolic Approach |
| Content Type | Text |
| Resource Type | Article |
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