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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Qianqian Huang Ru Huang Zhan Zhan Chunlei Wu Yingxin Qiu Yangyuan Wang |
| Copyright Year | 2012 |
| Description | Author affiliation: Institute of Microelectronics, Peking University, Beijing 100871, China (Qianqian Huang; Zhan Zhan; Chunlei Wu; Yingxin Qiu; Yangyuan Wang) |
| Abstract | In this paper, we have experimentally demonstrated an all-Si Pocket-Tunnel FET (Pocket-TFET) with steep subthreshold slope (SS) of 52mV/dec and high I ratio of $3.9×10^{6}$ based on the bulk silicon substrate by CMOS compatible process. It is the best experimental performance in the published silicon-based TFETs with a fully-depleted doping pocket layer at the source/channel interface. Compared with traditional TFET, through changing the drain layout, the extremely abrupt tunnel junction can be well achieved with the source pocket, resulting in the superior SS and I. In addition, the ambipolar effect can be also greatly reduced in the fabricated Pocket-TFET. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 676884 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6467740 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Junctions Silicon Doping Tunneling Temperature Current measurement |
| Content Type | Text |
| Resource Type | Article |
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