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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hailong Yao Yici Cai Wei Zhao |
| Copyright Year | 2012 |
| Description | Author affiliation: Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R. China (Hailong Yao; Yici Cai; Wei Zhao) |
| Abstract | As VLSI technology nodes continue to scale down, double patterning (DP) lithography has become the most promising interim solutions due to the delay in the deployment of next generation lithography (e.g., EUV). DP requires the partitioning of the layout patterns into two different masks, a procedure called layout decomposition. Layout decomposition is a key computational step that is necessary for double patterning technology. Existing works on layout decomposition are all single-threaded, which is not scalable in runtime and/or memory for large industrial layouts. This paper presents the first window-based parallel layout decomposition methods for improving both runtime and memory consumption. Experimental results are promising. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 3503142 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6466674 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Layout Lithography Runtime Servers Memory management Routing Color parallel computing double patterning lithography layout decomposition |
| Content Type | Text |
| Resource Type | Article |
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