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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Di Wu Xiaoxin Cui Wei Wei Rui Li Dunshan Yu Xiaole Cui |
| Copyright Year | 2012 |
| Description | Author affiliation: Peking University Shenzhen Graduate School, Shenzhen, 518055, China (Xiaole Cui) || Institute of Microelectronics, Peking University, Beijing, 100871, China (Di Wu; Xiaoxin Cui; Wei Wei; Rui Li; Dunshan Yu) |
| Abstract | Differential Power Analysis (DPA) is a powerful side channel attack method. Dual Rail Pre-charge Logic (DRP) is an effective circuit level DPA resistant countermeasure, however consumes more energy. Several adiabatic logic can resist differential power analysis attack while energy efficient. In this paper the comparison of DPA resistant ability for DRP logic and adiabatic logic will be presented and to make the comparison, a new criterion was introduced which could be used both for the DRP logic and adiabatic logic. Furthermore, the design issues for adiabatic logic will be discussed. Based on several standard cells and a full adder, the analysis results show that the ECRL logic has a good performance in DPA resistant ability (64%) as well as energy saving (83%). |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 326469 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6467785 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS integrated circuits Encryption Power demand Resistance Adders Energy consumption CMOS technology |
| Content Type | Text |
| Resource Type | Article |
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