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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhiru Zhang Deming Chen |
| Copyright Year | 2012 |
| Description | Author affiliation: Department of Electrical and Computer Engineering University of Illinois, Urbana-Champaign (Deming Chen) || School of Electrical and Computer Engineering, Cornell University (Zhiru Zhang) |
| Abstract | System-level synthesis compiles a complex application in a systemlevel description (such as SystemC) into a set of tasks to be executed on various processors, or a set of functions to be implemented in customized logic, as well as the communication protocols and the interface logic connecting different modules. Such capabilities are part of the so-called electronic system-level (ESL) design automation. ESL design automation has caught much attention from the industry recently. In general, it has been shown that the code density and simulation time can be improved by 10X and 100X, respectively, when moved to ESL from RTL. Such an improvement in efficiency is much needed for design in the deep submicron era. This paper identifies a set of key challenges in ESL design automation with major focus on high-level synthesis (HLS). We shall discuss existing and potential solutions to these challenges and outline research opportunities in the evolution of ESL design automation. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 312057 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6467670 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Optimization Design automation Field programmable gate arrays Estimation Memory management Hardware |
| Content Type | Text |
| Resource Type | Article |
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