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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hao Shu Jiang-Yi Shi Yue Hao Pei-Jun Ma Zhao Xu |
| Copyright Year | 2012 |
| Description | Author affiliation: Key Laboratory of Wide Band-gap Semiconductor Materials and Devices of Ministry of Education, Xidian University, Xi'an 710071, China (Hao Shu; Jiang-Yi Shi; Yue Hao; Pei-Jun Ma; Zhao Xu) |
| Abstract | Network-on-Chip has became a mainstream technology to solve the communication problems in Multi Processor SoC (MPSoC); and it has a greatly impact on system's performance, area and power consumption. In order to improve the performance of Network-on-Chip to fulfill the requirements of the MPSoC, this paper presents a dynamic adaptive NoC (DANoC) architecture, which can achieve the topology dynamic adaptation at run time. There are many features of DANoC, such as: the topology is simple and regular; the architecture is easy to extend in different network scales; the network traffic load is balanced. DANoC and Mesh have been verified under different network scales, injection rates and traffic patterns. The experimental results show that DANoC could effectively reduce latency and improve throughput, which is a simple and efficient Network-on-Chip. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 483984 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781467324748 |
| e-ISBN | 9781467324755 |
| DOI | 10.1109/ICSICT.2012.6467768 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-29 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Tiles Topology Computer architecture Network topology Routing Ports (Computers) Throughput |
| Content Type | Text |
| Resource Type | Article |
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