NDLI: Design, verification, and validation of self-checking software components

Content Provider	IEEE Xplore Digital Library
Author	Geoghegan, S.J. Avresky, D.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA (Geoghegan, S.J.; Avresky, D.)
Abstract	We propose a formal approach for adding fault detection to software. An assertion-based formalism is used to represent specifications and verify completeness and consistency. This specification is used to generate a flow graph, which is used to construct an exemplar-path tree. This representation is then used to generate an input set to exercise and verify the implementation. Previous software fault-tolerance (SFT) techniques emphasized algorithm-based fault tolerance (ABFT) which focused on detecting hardware faults that corrupted data structure contents. We propose a method that also detects hardware faults, which cause program flow errors. Our technique embeds two types of software checks. The first is based on the ABFT techniques described in the literature. The second type of check is used to detect faults that cause program flow errors. The exemplar-path tree provides information that can be used to predict a future program location, given the current location. During execution, program locations are recorded, along with expected locations, as determined from the exemplar-path tree. This information then is used to verify, that the future location is executed as expected. Hardware fault coverage has been estimated through experiments with the fault injection tool, SOFIT. Faults of differing durations were injected into memory, address bus, data bus, and CPU registers. The data presented, demonstrate the effectiveness of the method for detecting hardware faults.
Starting Page	420
Ending Page	426
File Size	924621
Page Count	7
File Format	PDF
ISBN	0780332555
DOI	10.1109/PCCC.1996.493666
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-03-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Hardware Fault tolerance Computer errors Flow graphs Tree graphs Software algorithms Data structures Embedded software Registers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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