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Content Provider | IEEE Xplore Digital Library |
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Author | Qianqian Huang Ru Huang Zhan Zhan Yingxin Qiu Wenzhe Jiang Chunlei Wu Yangyuan Wang |
Copyright Year | 2012 |
Description | Author affiliation: Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics, Peking University, Beijing 100871, China (Qianqian Huang; Ru Huang; Zhan Zhan; Yingxin Qiu; Wenzhe Jiang; Chunlei Wu; Yangyuan Wang) |
Abstract | In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current. |
File Size | 910852 |
File Format | |
ISBN | 9781467348720 |
ISSN | 2156017X |
e-ISBN | 9781467348713 |
e-ISBN | 9781467348706 |
DOI | 10.1109/IEDM.2012.6479005 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-12-10 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Silicon Junctions Logic gates Tunneling Switches Voltage measurement Electric fields |
Content Type | Text |
Resource Type | Article |
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