NDLI: Low cost VLSI design of a flexible FFT processor

Content Provider	IEEE Xplore Digital Library
Author	Jianing Su Zhenghao Lu
Copyright Year	2010
Description	Author affiliation: Department of Electronics and Information Science, Soochow University, Suzhou, Jiangsu, 215006, China (Jianing Su; Zhenghao Lu)
Abstract	In this paper, a low-cost VLSI implementation of a pipeline fast Fourier transform (FFT) processor capable of supporting from 1k to 32k FFT sizes is presented. The $radix-2^{2}/2^{3}$ based pipeline structure reduces the steps of normal complex multiplications, and the single-path delay feedback (SDF) memory access method ensures a minimum (N-1) memory words to get the FFT results. As for the data-path in the pipeline FFT processor, the hybrid floating point data-scaling scheme is adopted to achieve enough signal-to-quantization-noise ratio with minimum data width and RAM requirements. A 1k–32k flexible FFT core is implemented in the Altera FPGA, results show that our proposed scheme is suitable for applications where flexible large size FFT processor is needed such as digital video broadcasting, wireless networks etc.
Starting Page	488
Ending Page	490
File Size	315354
Page Count	3
File Format	PDF
ISBN	9781424457977
e-ISBN	9781424457984
DOI	10.1109/ICSICT.2010.5667371
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines OFDM Discrete Fourier transforms Digital video broadcasting Delay Field programmable gate arrays Algorithm design and analysis hybrid floating point Fast Fourier transform (FFT) flexible pipeline FFT single-path delay feedback (SDF)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Notice of Violation of IEEE Publication PrinciplesEfficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor

High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications

FPGA implementation of Hilbert transform via $radix-2^{2}$ pipelined FFT processor

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA

An Efficient FFT Processor for DAB Receiver Using Circuit-Sharing Pipeline Design

FPGA implementation of Fast Fourier Transform

FFT Processor IP Cores synthesis on the base of configurable pipeline architecture

FPGA Implementation of High Speed FFT Algorithm Based on Split-Radix

Low cost VLSI design of a flexible FFT processor

Similar Documents

Notice of Violation of IEEE Publication PrinciplesEfficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor

High-speed, Low Cost Parallel Memory-Based FFT Processors for OFDM Applications

FPGA implementation of Hilbert transform via $radix-2^{2}$ pipelined FFT processor

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

An efficient MIMO-OFDM radix-2 Single-Path Delay Feedback FFT implementation on FPGA

An Efficient FFT Processor for DAB Receiver Using Circuit-Sharing Pipeline Design

FPGA implementation of Fast Fourier Transform

FFT Processor IP Cores synthesis on the base of configurable pipeline architecture

FPGA Implementation of High Speed FFT Algorithm Based on Split-Radix

Low cost VLSI design of a flexible FFT processor