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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiaowei Han Chen, S.L. Lihua Wu Yan Zhao Yan Li |
| Copyright Year | 2010 |
| Description | Author affiliation: Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China (Xiaowei Han; Chen, S.L.; Lihua Wu; Yan Zhao; Yan Li) |
| Abstract | A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5µm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement Block RAM in implementing the data storage logic of many applications. The functionality and performance of the Distributed RAM have been proven in our test circuit. Comparing with the published data on the Distributed RAM in Xilinx Spartan FPGA, our Distributed RAM average access time has about 21% improvement. |
| Starting Page | 306 |
| Ending Page | 308 |
| File Size | 356738 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424457977 |
| e-ISBN | 9781424457984 |
| DOI | 10.1109/ICSICT.2010.5667746 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Field programmable gate arrays Table lookup Arrays Timing Distributed databases Multiplexing |
| Content Type | Text |
| Resource Type | Article |
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