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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yoshimi, M. Cauchy, X. Maleville, C. |
| Copyright Year | 2010 |
| Description | Author affiliation: Soitec Asia, Shin-Tokyo Bldg., 3-3-1, Marunouchi, Chiyoda-ku, 100-0005, Japan (Yoshimi, M.) || Soitec, Parc Technologique des Fontaines, 38926 Bernin, Crolle Cedex, France (Cauchy, X.; Maleville, C.) |
| Abstract | Ultra-thin SOI wafer technologies designed for 22/20nm CMOS are presented. It is stressed that planar, non-doped, and fully-depleted (FD) SOI structures are realistic options that not only solve various scaling issues, but also provide simplicity and flexibility in the device process and the circuit design. To realize 22/20nm planar FD-SOI CMOS, 300mm SOI wafer process by Smart Cut™ [1] has been optimized, focusing on the uniformity of Si film thickness, and adjusting thickness of buried oxide (BOX). It is shown that thickness variation of a 12nm-thick Si film can be controlled within +/− 2.5% for the whole wafer area. Also, buried-oxide (BOX) can be reduced down to 10nm while maintaining high bonding quality, which is expected to provide 22/20nm FD-SOI CMOS with additional advantages, such as improved short channel effect, multi-threshold voltages, and SOI-bulk hybrid structure. It is also shown that these technologies are extending planar CMOS roadmap beyond 22/20nm nodes. |
| Starting Page | 997 |
| Ending Page | 998 |
| File Size | 455860 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424457977 |
| e-ISBN | 9781424457984 |
| DOI | 10.1109/ICSICT.2010.5667514 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-01 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Silicon Films CMOS integrated circuits CMOS technology Analog circuits Very large scale integration Scalability |
| Content Type | Text |
| Resource Type | Article |
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